1. Field of the Invention
The present invention relates to a semiconductor device, and particularly to a structure of an internal voltage generating circuit for internally generating a voltage at a desired level.
2. Description of the Background Art
FIG. 47 schematically shows a whole structure of a conventional semiconductor memory device. In FIG. 47, the semiconductor memory device includes a memory cell array 100 having a plurality of memory cells MC arranged in rows and columns. In memory cell array 100, word lines WL are arranged corresponding to the rows of memory cells MC, respectively, and bit line pairs BLP are arranged corresponding to the columns of memory cells MC, respectively. Memory cells MC are arranged corresponding to crossings between bit line pairs BLP and word lines WL, respectively.
The semiconductor memory device further includes an address input buffer 200 which takes in an externally supplied address signal ADD to produce an internal address signal, a row select circuit 250 which drives a word line WL corresponding to an addressed row in memory cell array 100 to the selected state in accordance with an internal row address signal from address input buffer 200, a sense amplifier circuit 300 which senses, amplifies and latches data of the memory cells connected to the selected row, a column select circuit 350 which selects an addressed column in memory cell array 100 in accordance with an internal column address signal from address input buffer 200, and an I/O circuit 400 which transmits data to and from the memory cell in the column selected by column select circuit 350.
Row select circuit 250 includes a row decoder for decoding the internal row address signal from address input buffer 200, and a word line drive circuit for driving the word line by the output signal of the row decoder to the selected state. The column select circuit 350 includes a column decoder for decoding the internal column address signal from address input buffer 200, and an I/O gate circuit for connecting the addressed column in the memory cell array to an internal data bus (not clearly shown) in accordance with a column select signal from the column decoder. Sense amplifier circuit 300 includes sense amplifiers which are provided corresponding to bit line pairs BLP, and differentially amplify potentials on the corresponding bit line pairs when made active, respectively.
Semiconductor memory device further includes an internal power supply circuit 500 which down-converts an externally supplied power supply voltage Vext to produce internal power supply voltages Vccp and Vccs. Internal power supply voltage Vccp produced by internal power supply circuit 500 is supplied to peripheral circuits, i.e., address input circuit 200, row select circuit 250, column select circuit 350 and I/O circuit 400. Internal power supply voltage Vccs is supplied to sense amplifier circuit 300.
Internal power supply voltage Vccp is at a level higher than or equal to that of internal power supply voltage Vccs. By applying high internal power supply voltage Vccp to the peripheral circuits, the peripheral circuits are operated fast. Meanwhile, by applying internal power supply voltage Vccs lower than internal power supply voltage Vccp to sense amplifier circuit 300, a charge/discharge current of the bit line is reduced and the bit line signal amplitude is also reduced, whereby a fast access operation is achieved. If the device is a DRAM (Dynamic Random Access Memory), memory cell MC is formed of an access transistor and a capacitor. In this case, application of a high voltage to an insulating film of this capacitor is prevented so that the reliability of capacitor insulating film can be assured. Further, it is possible to ensure a reliability of the word lines subjected to a 1.5 times higher voltage than voltage Vccs.
In address input buffer 200 and I/O circuit 400, external power supply voltage Vext is used for portions interfaced to an external device, although not shown in FIG. 47.
As a storage capacity of the semiconductor memory device increases, MOS transistors as the components are miniaturized accordingly. However, external devices such as a processor and a logic have not been highly miniaturized compared with the semiconductor memory devices, and therefore relatively high operation power supply voltages are used for maintaining intended operation speeds. It is necessary to maintain compatibility in the power supply voltage with previous-generation semiconductor memory devices. Accordingly, external power supply voltage Vext is lowered by internal power supply circuit 500 to produce internal power supply voltages Vccp and Vccs so that the compatibility of the system power supply voltage is maintained while maintaining the compatibility with previous-generation semiconductor memory devices.
FIG. 48 schematically shows a structure of internal power supply circuit 500 shown in FIG. 47. In FIG. 48, internal power supply circuit 500 includes a reference voltage generating circuit 502s generating a reference voltage Vrefs, a reference voltage generating circuit 502p generating a reference voltage Vrefp, a voltage down converter 504s which is supplied with a current from a node receiving external power supply voltage Vext and adjusting a voltage level of internal (sense) power supply voltage Vccs in accordance with a difference between internal power supply voltage Vccs and reference voltage Vrefs, and a voltage down converter 504p which is supplied with a current from a node receiving external power supply voltage Vext and adjusting a voltage level of internal power supply voltage Vccp in accordance with a difference between internal power supply voltage Vccp and reference voltage Vrefp. Reference voltage generating circuit 502s and voltage down converter 504s form a sense power supply circuit producing an internal power supply voltage for the sense amplifiers. Reference voltage generating circuit 502p and voltage down converter 504p form a peripheral power supply circuit producing internal power supply voltage Vccp for the peripheral circuits. The sense power supply circuit and the peripheral power supply circuit are made independent from each other for the following reasons.
During an operation of sense amplifier circuit 300 shown in FIG. 47, bit line pairs BLP connected to a selected word line WL are charged and discharged. The charge/discharge current during the operation of the sense amplifiers is relatively large, and voltage down converter 504s of the sense power supply circuit is required to have a large current drive capability for compensating for this large current consumption. However, only the charging and discharging of the bit line pair BLP are required, and fast recovering of internal power supply voltage (which will be referred to as a "sense power supply voltage") Vccs to the initial state is not required. Therefore, a significantly fast responsibility is not required in voltage down converter 504s. In contrast, a sufficiently fast responsibility is required in voltage down converter 504p of the peripheral power supply circuit because fast compensation must be made for a variation in internal power supply voltage (which will be referred to as a "peripheral power supply voltage") Vccp so as to achieve fast and stable operation of the peripheral circuits. Meanwhile, the peripheral circuits in operation consume a current smaller than that in the operation of the sense amplifier. Accordingly, voltage down converter 504p of the peripheral power supply circuit is required to have a fast responsibility although the required drive current is relatively small. For satisfying these different required characteristics, the sense power supply circuit and the peripheral power supply circuit are arranged independently of each other.
The semiconductor memory device includes the independent power supply circuits for the peripheral circuit and for the sense amplifier circuit. Since sense power supply voltage Vccs and peripheral power supply voltage Vccp are different in voltage level from each other, reference voltages Vrefs and Vrefp which determine the voltage levels of power supply voltages Vccs and Vccp are generated from independent reference voltage generating circuits 502s and 502p, respectively. This results in a problem that the reference voltage generating circuits occupy a large area in internal power supply circuit 500, and the occupied area cannot be reduced. Due to provision of independent reference voltage generating circuits 502s and 502p, trimming of the voltage levels of reference voltages Vrefs and Vrefp must be performed independently of each other, and the voltage trimming requires a long time.
FIG. 49 shows the structure of voltage down converters 504s and 504p shown in FIG. 48. Sense voltage down converter 504s generating power supply voltage Vccs and peripheral voltage down converter 504p generating peripheral power supply voltage Vccp have the same structure, and therefore FIG. 49 representatively shows voltage down converter 504.
In FIG. 49, voltage down converter 504 includes a comparator 505a which compares internal power supply voltage Vcc on an internal power supply line 505d with reference voltage Vref, a current drive circuit 505b which is formed of an n channel MOS transistor and supplies a current from the external power supply node receiving external power supply voltage Vext to internal power supply line 505d in accordance with the output signal of comparator 505a, and a reset transistor 505c which is formed of a p channel MOS transistor and transmits external power supply voltage Vext to internal power supply line 505d in response to a power-on detection signal /POR after power-on. Power-on detection signal /POR is kept active at L-level until external power supply voltage Vext reaches predetermined voltage level or a stable state after the power-on, and is used for initialization of internal circuit nodes.
Comparator 505a is typically formed of a differential amplifier, and receives internal power supply voltage Vcc and reference voltage Vref on its positive and negative inputs, respectively. When internal power supply voltage Vcc is higher than reference voltage Vref, comparator 505a generates the output signal at H-level, and current drive transistor 505b keeps the off state. When internal power supply voltage Vcc is lower than reference voltage Vref, comparator 505a generate the output signal at a low level corresponding to a difference between these voltages Vcc and Vref, and a conductance of current drive transistor 505b increases. Thereby, a current is increasingly supplied from the external power supply node to internal power supply line 505d, and the voltage level of internal power supply voltage Vcc rises. In the structure of voltage down converter 504 shown in FIG. 49, therefore, internal power supply voltage Vcc is maintained substantially at the voltage level of reference voltage Vref.
FIG. 50 shows a relationship between internal power supply voltage Vcc, reference voltage Vref and external power supply voltage Vext. In FIG. 50, the abscissa gives the voltage level of external power supply voltage Vext, and the ordinate gives the respective voltages. Reference voltage Vref is produced from external power supply voltage Vext. Reference voltage Vref is generally produced by a constant current source and a resistance circuit. The voltage level of reference voltage Vref rises in accordance with the level of external power supply voltage Vext when the level of external power supply voltage Vext is low. When external power supply voltage Vext reaches or exceeds a predetermined voltage level, reference voltage Vref maintains a constant level of a voltage Va independently of the voltage level of external power supply voltage Vext. Internal power supply voltage Vcc is produced based on a comparison between reference voltage Vref and the voltage on internal power supply line 505d. The voltage level of internal power supply voltage Vcc is substantially equal to the voltage level of reference voltage Vref, but is slightly lower than the voltage level of reference voltage Vref due to a channel resistance of current drive transistor 505b.
When power supply voltage Vext is made on, the voltage level of external power supply voltage Vext rises, and correspondingly the voltage level of reference voltage Vref rises. Comparator 505a and current drive transistor 505b adjusts the voltage level of internal power supply voltage Vcc in accordance with a result of comparison between the voltage on internal power supply line 505d and reference voltage Vref Therefore, the voltage level of internal power supply voltage Vcc rises corresponding to rising of the voltage level of reference voltage Vref caused in accordance with power-on and subsequent rise of the voltage level of external power supply voltage Vext. When reference voltage Vref reaches the constant voltage level and attains the stable state, internal power supply voltage Vcc also reaches a stable voltage level. Thus, the voltage level of internal power supply voltage Vcc is stabilized after the voltage level of reference voltage Vref is stabilized, and therefore it is impossible to rapidly stabilize internal power supply voltage Vcc after starting of supply of external power supply voltage Vext. Accordingly, reset transistor 505c is used for raising the voltage level on internal power supply line 504 in accordance with the voltage level of external power supply voltage Vext for a predetermined period after the power-on.
FIG. 51 shows a change in internal power supply voltage upon power-on. In FIG. 51, the power is on at time t0 and the voltage level of external power supply voltage Vext rises. In this state, power-on detection signal /POR maintains the L-level. Therefore, reset transistor 505c is turned on, and voltage Vcc on internal power supply line 505d changes in accordance with the voltage level of external power supply voltage Vext.
At time t1, external power supply voltage Vext attains a level of a predetermined voltage Vb so that power-on detection signal /POR attains the inactive state of H-level, and reset transistor 505c is turned off. Thereafter, comparing circuit 505a and current drive transistor 505b drive internal power supply voltage Vcc to the level of reference voltage Vref.
Owing to provision of reset transistor 505c, the voltage level of internal power supply voltage Vcc on internal power supply line 505d can be rapidly raised after the power-on, and can be stabilized at the predetermined voltage level (i.e., level of reference voltage Vref) at an early time.
In the above case, internal power supply line 505d is coupled to the node receiving the external power supply voltage until power-on detection signal /POR attains the inactive state of H-level after the power-on. Therefore, an unnecessarily high voltage is applied to internal power supply line 505d due to, e.g., noises, which may result in instantaneous breakdown, i.e., breakdown of circuits utilizing internal power supply voltage Vcc on internal power supply line 505d and/or degradation of the reliability thereof (due to application of large voltage stresses upon each power-on). Particularly, if voltage down converter 504 is activated only when the internal circuits operate, voltage Vcc on internal power supply line 505d must be driven to the predetermined level in accordance with an independent standby voltage down converter which has a small current drive capability and normally operates. For rapidly stabilizing internal power supply voltage Vcc, complicated adjustment of timing of power-on detection signal /POR is required, and therefore it is difficult to ensure a reliability of the internal circuits. Further, if power-on detection signal /POR is held in the active state at L-level for a long period as shown by broken line in FIG. 51, internal power supply voltage Vcc is driven to a voltage level higher than reference voltage Vref so that unnecessarily high voltages is applied to the internal circuits, resulting in deterioration of element characteristics or breakdown of circuit elements.
FIG. 52 shows temperature dependency of reference voltage Vref and internal power supply voltage Vcc. In FIG. 52, the abscissa give a temperature T, and the ordinate gives a voltage V. As shown in FIG. 52, the reference voltage Vref and internal power supply voltage Vcc have positive temperature characteristics, and rise with increasing of temperature T. The purposes of these characteristics are to prevent deterioration of element characteristics due to trap of produced hot carriers in gate insulating film of insulated gate field effect transistors (MOS transistors) included in the internal circuits in a low temperature operating region, and to compensate for lowering in operation speed in operation at a high temperature, due to reduction in drain current by the increased channel-resistance by hot carriers. However, the positive temperature characteristics of internal power supply voltage Vcc causes the following problem in a low temperature region. The absolute value of the threshold voltage of MOS transistor increases in a low temperature region. Therefore, when the gate voltage of the MOS transistor lowers in the low temperature region, an effective gate-source voltage of the MOS transistor decreases in absolute value, so that the MOS transistor cannot operate fast or may malfunction (may not be turned on completely). Particularly, a sense amplifier included in the sense amplifier circuit amplifies a difference between the bit line voltage at an intermediate level and the sense power supply voltage Vccs. Therefore, the gate-source voltage of the MOS transistor forming the sense amplifier takes the maximum value of (Vccs-Vccs/2) when the operation starts, and therefore the sense amplifier is remarkably affected by increase in absolute value of the threshold voltage of the MOS transistor and decrease in sense power supply voltage Vccs. If the sense power supply voltage Vccs is optimized for the low temperature region, sense power supply voltage Vccs becomes excessively high in the high temperature operation so that breakdown or deterioration of the gate insulating film may occur.
For fast operation of the sense amplifier circuit, it can be considered that the level of sense power supply voltage Vccs applied to the sense amplifier circuit may be raised at the start of the sensing operation. In this case, the sense amplifier power supply voltage for the sense amplifier circuit is raised to the level of peripheral power supply voltage Vccp, and the raised voltage is stored in a capacitor. In the sensing operation, charges accumulated in the capacitor are utilized for the sensing operation, whereby the sensing operation can be performed fast. In this case, however, the capacitor for raising the voltage must be arranged on the sense power supply line supplying sense amplifier power supply voltage Vccs. If the capacitance value of this capacitor is determined with a margin, the capacitor occupies an unnecessarily large area, resulting in disadvantageous increase in chip area.
For reducing a current consumption of the whole system, external power supply voltage Vext is set to a low level. If the voltage level of external power supply voltage Vext is lowered to a level near a voltage Va shown in FIG. 50 and if a difference between external power supply voltage Vext and internal power supply voltage Vcc decreases, the source-drain voltage of current drive transistor 505b shown in FIG. 49 decreases, and the current supply capability of current drive transistor 505b decreases so that it is impossible to compensate for lowering of internal power supply voltage Vcc when internal power supply voltage Vcc changes, and internal power supply voltage Vcc cannot be stably held at the predetermined voltage level. As described below, the output signal of the comparator forms another cause of reduction of the quantity of current supplied from the external power supply node to the internal power supply line when external power supply voltage Vext lowers.
FIG. 53 shows a structure of comparator 505a shown in FIG. 49. In FIG. 53, comparator 505a includes a p channel MOS transistor PQ1 which is connected between the external power supply node and a node NDA and has a gate connected to a node NDB, a p channel MOS transistor PQ2 which is connected between the external power supply node and node NDB and has a gate connected to node NDB, an n channel MOS transistor NQ1 which is connected between nodes NDA and NDC and has a gate receiving reference voltage Vref, an n channel MOS transistor NQ2 which is connected between nodes NDB and NDC and has a gate receiving internal power supply voltage Vcc, and an n channel MOS transistor NQ3 which is connected between node NDC and a ground node and has a gate receiving an activating signal ACT. Node NDA is connected to the gate of current drive transistor 505b.
MOS transistors PQ1 and PQ2 form a current mirror circuit, and transmit the currents of the same magnitude to MOS transistors NQ1 and NQ2, respectively. MOS transistor NQ3 is a current source transistor, and restricts the operating current of comparator 505a. Activating signal ACT is activated when circuitry connected to internal power supply line 505d operates to consume internal power supply voltage Vcc.
In the structure of comparator 505a shown in FIG. 53, the voltage level on node NDC is higher than the ground voltage level due to the channel resistance of MOS transistor NQ3. If the back gates of MOS transistors NQ1 and NQ2 are connected to the ground voltage level, the back gate effect of MOS transistors NQ1 and NQ2 increases when the voltage level on node NDC rises so that the threshold voltages of MOS transistors NQ1 and NQ2 increase to reduce the drive currents thereof. The lowest attainable potential on node NDA is equal to the voltage level on node NDC, and is higher than the ground voltage level. Node NDA is connected to the gate of current drive transistor 505b. Therefore, as the voltage level of external power supply voltage Vext lowers, the gate-source voltage of current drive transistor 505b further decreases, and the current supply capability of current drive transistor 505b reduces. Accordingly, as the difference between the external power supply voltage Vext and the internal power supply voltage Vcc decreases, the source-drain voltage and the gate-source voltage of current drive transistor 505b decrease so that the current supply capability of current drive transistor 505b further reduces. For increasing the current supply capability of current drive transistor 505b, a gate width W thereof must be set to several millimeters, resulting in disadvantageous increase in area occupied by the element.
Activating signal ACT must be activated in consumption of internal power supply voltage Vcc on internal power supply line 505d. It is necessary to make an area occupied by the circuit producing the activating signal ACT as small as possible.
Instead of the voltage down converter which is selectively activated in response to activating signal ACT as shown in FIG. 53, such a voltage down converter may be employed that operates even during standby to compensate for a leak current during standby. In this structure, a bias voltage at a constant voltage level is used instead of activating signal ACT. In this case, the voltage level on node NDC further increases (because the conductance of the current source transistor decreases), and such a problem becomes more remarkable that the current supply capability of the current drive transistor is reduced if external power supply voltage Vext is low. Accordingly, it is necessary to employ a current drive transistor occupying a large area for compensating for a leak current during standby.
In the conventional internal power supply circuit, as described above, it is impossible to produce stably an internal power supply voltage over wide ranges of operation parameters (the operation temperature and the power supply voltage) with a small area and a small current consumption.